Transfer Error Status Register (Ltesr) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 10-15 describes LURT fields.
Bits Name
0–7 LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according
to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given MRTPR[PTP] = 32, the
LURT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required service
period of 15.6 µs.
Note that the reset value (0x00) sets the maximum period to 256 x MRTPR[PTP] system clock cycles.
8–31 — Reserved
10.3.1.9

Transfer Error Status Register (LTESR)

The transfer error status register (LTESR) indicates the cause of an error or event. LTESR, shown in
Figure 10-13, is a write-1-to-clear register. Reading LTESR occurs normally; however, write operations
can clear but not set bits. A bit is cleared whenever the register is written, and the data in the corresponding
bit location is a 1. For example, to clear only the write protect error bit (LTESR[WP]) without affecting
other LTESR bits, 0x0400_0000 should be written to the register. After any error/event reported by
LTESR, LTEATR[V] must be cleared for LTESR to updated again. Note that error statuses are only
reflected in LTESR if they have been enabled in LTEDR.
Offset 0x0B0
0 1 2
R
BM FCT PAR
W
Reset
16
R
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 10-15. LURT Field Descriptions
TimerPeriod
3 4 5 6
— WP —
—
Figure 10-13. Transfer Error Status Register (LTESR)
Description
LURT
= --------------------------------------------- -
⎛
Fsystemclock
--------------------------------------- -
⎝
[ ]
MRTPR PTP
7 8 9 10
ATM
ATMW —
R
All zeros
All zeros
Enhanced Local Bus Controller
⎞
⎠
Access: w1c
11 12 13
CS —
29 30
UCC
15
31
CC
10-25