Repeated Start Condition; Stop Condition; Protocol Implementation Details; Transaction Monitoring—Implementation Details - Freescale Semiconductor MPC8313E Family Reference Manual

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I C Interfaces
17.4.1.3

Repeated START Condition

Figure 17-8 shows a repeated START condition, which is generated without a STOP condition that can
terminate the previous transfer. The master uses this method to communicate with another slave or with
the same slave in a different mode (transmit/receive mode) without releasing the bus.
17.4.1.4

STOP Condition

The master can terminate the transfer by generating a STOP condition to free the bus. A STOP condition
is defined as a low-to-high transition of the SDAn signal while SCLn is high. For more information, see
Figure 17-8. Note that a master can generate a STOP even if the slave has transmitted an acknowledge bit,
at which point the slave must release the bus. The STOP condition is initiated by a software write that
clears I2CnCR[MSTA].
As described in Section 17.4.1.3, "Repeated START Condition,"
condition followed by a calling address without generating a STOP condition for the previous transfer.
This is called a repeated START condition.
17.4.1.5

Protocol Implementation Details

The following sections give details of how aspects of the protocol are implemented in the I
17.4.1.5.1 Transaction Monitoring—Implementation Details
The different conditions of the I
• START conditions are detected when an SDAn fall occurs while SCLn is high.
• STOP conditions are detected when an SDAn rise occurs while SCLn is high.
• Data transfers in progress are canceled when a STOP condition is detected or if there is a slave
address mismatch. Cancellation of data transactions resets the clock module.
• The bus is detected to be busy upon the detection of a START condition and idle upon the detection
of a STOP condition.
17.4.1.5.2 Control Transfer—Implementation Details
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The I C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines
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of the I C. The SCLn output is pulled low as determined by the internal clock generated in the clock
module. The SDAn output can change only at the midpoint of a low cycle of the SCLn, unless it is
performing a START, STOP, or repeated START condition. Otherwise, the SDAn output is held constant.
SDAn is negated when one or more of the following conditions are true:
• Master mode
— Data bit (transmit)
— ACK bit (receive)
— START condition
— STOP condition
— Repeated START condition
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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C data transfers are monitored as follows (see
the master can generate a START
Figure 17-8):
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C module.