Power Management Controller Configuration Register 1 (Pmccr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Offset 0x00B08

defines the bit fields of PMCMR.

GPIO, PCI(PME), USB,

eTSEC1, eTSEC2, Timer, Int1,

The user is also required to enable the PMC interrupt in the programmable

interrupt controller by setting SIMSR_L[PMC].

Power Management Controller Configuration Register 1 (PMCCR1)

The power management controller configuration register 1 (PMCCR1), shown in

sequencing of the device into its low power state including PME (power management event) signaling,

toggling of the external power switch, and indication of current and desired power states.

Offset 0x00B0C

Figure 5-54. Power Management Controller Configuration Register 1

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 5-53. Power Management Controller Mask Register

Table 5-68. PMCMR Bit Settings

Reserved. Write has no effect, read returns 0.

Wake-up event masking.

0 Mask wake-up events from Int2, Int1, Timer, eTSEC2, eTSEC1, USB, PCI, or

GPIO, respectively.

1 Do not mask wake-up events

Power management controller interrupt enable.

0 PMC interrupt request (PMCI) is disabled.

1 PMC interrupt request (PMCI) is enabled.

LLPEN PME_EN ASSERT_PME POWER_OFF

eTSEC2 Timer

System Configuration

Access: Read/Write

5-54, controls the

Access: Read/Write

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