Interrupt Configuration - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Interrupt Configuration

shows the interrupt configuration.

System Bus Arbiter

System Bus Arbiter

The interrupt controller allows masking of each interrupt source. When an unmasked interrupt source is

pending in the SIPNR register, the interrupt controller sends an interrupt request to the core. When an

interrupt is taken, the interrupt mask bit in the machine state register is cleared to disable further interrupt

requests to the PowerPC core until software can handle them.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 8-25. Interrupt Structure

Integrated Programmable Interrupt Controller (IPIC)

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