External Signals Description - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Internal loop back mode is selected through the loop back bit in the MACCFG1 register. See
Section 15.7.1, "Interface Mode Configuration,"
15.4

External Signals Description

This section defines the eTSEC interface signals. The buses are described using the bus convention used
in IEEE 802.3 because the PHY follows this same convention. (That is, TxD[3:0] means 0 is the lsb.) Note
that except for external physical interfaces the buses and registers follow a big-endian format, where 0
denotes the msb.
Each eTSEC network interface supports multiple options:
• The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface)
and supports both a data and a management interface to the PHY (transceiver) device. The MII
option supports both 10- and 100-Mbps Ethernet rates.
• The RGMII, RTBI, and RMII options are reduced-pin implementations of the GMII, TBI, and MII
interfaces, respectively.
• SGMII interfaces are offered via the SerDes interface signals.
• 1588 timer signals
Table 15-1 lists the network interface signals.
Signal Name
TSEC n _COL MII—collision, input
TSEC n _CRS MII—carrier sense, input
TSEC n _GTX_CLK RTBI, RGMII—inverted transmit clock feedback, output
MII, RMII—transmit clock feedback when transmission is enabled, zero otherwise, output
EC_GTX_CLK125 Oscillator source for RGMII, RTBI transmit clock, input, shared by all eTSECs
EC_MDC Management clock, output.
EC_MDIO Management data, bidirectional.
TSEC n _RX_CLK MII, RGMII—receive clock, input
TSEC n _RX_DV
MII—receive data valid, input
RGMII (RX_CLK rising)—receive data valid, input
RGMII (RX_CLK falling)—receive error, input
RTBI (RX_CLK rising)—receive code group (RCG) bit 4, input
RTBI (RX_CLK falling)—receive code group (RCG) bit 9, input
RMII—CRS_DV carrier sense/data valid, input
TSEC n _RXD[3:0] MII—Receive data bits 3:0, input
RGMII (RX_CLK rising) —Receive data bits 3:0, input
RGMII (RX_CLK falling)—Receive data bits 7:4, input
RTBI (RX_CLK rising)—RCG bits 3:0, input
RTBI (RX_CLK falling)—RCG bits 8:5, input
RMII—RXD[1:0] receive data bits, input
RMII—RXD[3:2] are unused
TSEC n _RX_ER MII, RMII—Receive error, input
RGMII, RTBI—Unused
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-6
Table 15-1. eTSEC n Network Interface Signal Properties
for details.
Function
Reset
State
—
—
0
—
0
Hi-Z (input)
—
—
—
—
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