Freescale Semiconductor MPC8313E Family Reference Manual page 45

Figure
Number
10-69 Multiplexed Address/Data Bus for 26-Bit Addressing ....................................................... 10-91
10-70 Non-Multiplexed Address and Data Buses ......................................................................... 10-92
10-71 Local Bus Peripheral Hierarchy for High Bus Speeds........................................................ 10-92
10-72 GPCM Address Timings ..................................................................................................... 10-93
10-73 GPCM Data Timings........................................................................................................... 10-93
10-74 Interface to Different Port-Size Devices ............................................................................. 10-95
10-75 Single-Beat Read Access to FPM DRAM ........................................................................ 10-101
10-76 Single-Beat Write Access to FPM DRAM ....................................................................... 10-102
10-77 Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)............................ 10-103
10-78 Refresh Cycle (CBR) to FPM DRAM .............................................................................. 10-104
10-79 Exception Cycle ................................................................................................................ 10-105
10-80 Interface to ZBT SRAM ................................................................................................... 10-106
11-1 I/O Sequencer Block Diagram .............................................................................................. 11-1
11-2 PCI Outbound Translation Address Registers (POTARn) .................................................... 11-3
11-3 PCI Outbound Base Address Registers (POBARn).............................................................. 11-3
11-4 PCI Outbound Comparison Mask Registers (POCMRn) ..................................................... 11-4
11-5 Power Management Control Register (PMCR) .................................................................... 11-5
11-6 Discard Timer Control Register (DTCR).............................................................................. 11-6
11-7 Outbound PCI Memory Address Translation ....................................................................... 11-8
12-1 DMA/Messaging Unit Block Diagram ................................................................................. 12-1
12-2 Outbound Message Interrupt Status Register (OMISR) ....................................................... 12-3
12-3 Outbound Message Interrupt Mask Register (OMIMR)....................................................... 12-4
12-4 Inbound Message Registers (IMR0, IMR1).......................................................................... 12-5
12-5 Outbound Message Registers (OMR0–OMR1) .................................................................... 12-5
12-6 Outbound Doorbell Register (ODR) ..................................................................................... 12-6
12-7 Inbound Doorbell Register (IDR) ......................................................................................... 12-7
12-8 Inbound Message Interrupt Status Register (IMISR)............................................................ 12-7
12-9 Inbound Message Interrupt Mask Register (IMIMR) ........................................................... 12-8
12-10 DMA Mode Register (DMAMRn) ....................................................................................... 12-9
12-11 DMA Status Register (DMASRn) ...................................................................................... 12-11
12-12 DMA Current Descriptor Address Register (DMACDARn).............................................. 12-12
12-13 DMA Source Address Register (DMASARn) .................................................................... 12-13
12-14 DMA Destination Address Register (DMADARn) ............................................................ 12-13
12-15 DMA Byte Count Register (DMABCRn)........................................................................... 12-14
12-16 DMA Next Descriptor Address Register (DMANDARn) .................................................. 12-14
12-17 DMA General Status Register (DMAGSR)........................................................................ 12-15
12-18 DMA Controller Block Diagram ........................................................................................ 12-16
12-19 DMA Chain of Segment Descriptors .................................................................................. 12-19
13-1 PCI Controller Block Diagram ............................................................................................. 13-2
13-2 PCI Interface External Signals.............................................................................................. 13-5
13-3 PCI_CONFIG_ADDRESS Register ................................................................................... 13-13
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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