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For example, if a write transaction is desired with a size of one word (4 bytes), then the second, third, and
fourth beats of data are not written to DRAM, as the width of the data bus is 32 bits.
Table 9-35
lists the data beat sequencing to and from the DDR SDRAM and the data queues for each of
the possible transfer sizes with each of the possible starting double-word offsets. All underlined
double-word offsets are valid for the transaction.
Transfer Size
1 double word
2 double words
3 double words
1
All underlined Double-word offsets are valid for the transaction.
9.5.10
Page Mode and Logical Bank Retention
The DDR memory controller supports an open/closed page mode with an allowable open page for each
logical bank of DRAM used. In closed page mode for DDR SDRAMs, the DDR memory controller uses
the SDRAM auto-precharge feature, which allows the controller to indicate that the page must be
automatically closed by the DDR SDRAM after the READ or WRITE access. This is performed using
MA[10] of the address during the COMMAND phase of the access to enable auto-precharge.
Auto-precharge is non-persistent in that it is either enabled or disabled for each individual READ or
WRITE command. It can, however, be enabled or disabled separately for each chip select.
When the DDR memory controller operates in open page mode, it retains the currently active SDRAM
page by not issuing a precharge command. The page remains opens until one of the following conditions
occurs:
•
Refresh interval is met.
•
The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
•
There is a logical bank row collision with another transaction that must be issued.
Page mode can dramatically reduce access latencies for page hits. Depending on the memory system
design and timing parameters, using page mode can save two to three clock cycles for subsequent burst
accesses that hit in an active page. Also, better performance can be obtained using more banks, especially
in systems which use many different channels. Page mode is disabled by clearing
DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN].
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-35. Memory Controller—Data Beat Ordering
Starting Double-Word Offset
0
1
2
3
0
1
2
0
1
DDR Memory Controller
1
Double-Word Sequence
DRAM and Queues
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
0 - 1 - 2 - 3
1 - 2 - 3 - 0
to/from
9-51
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