Freescale Semiconductor MPC8313E Family Reference Manual page 344

e300 Processor Core Overview
Bits Name
11 DPM Dynamic power management enable
0 Dynamic power management is disabled
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect
12–15 — Reserved
16 ICE Instruction cache enable
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were
1 The instruction cache is enabled
17 DCE Data cache enable
0 The data cache is neither accessed nor updated. All pages are accessed as if they were marked
1 The data cache is enabled
18 ILOCK Instruction cache lock
0 Normal operation
1 The entire instruction cache is locked (that is, all eight ways of the cache are locked). A locked cache
To prevent locking during a cache access, an isync instruction must precede the setting of ILOCK.
19 DLOCK Data cache lock
0 Normal operation
1 The entire data cache is locked (that is, all eight ways of the cache are locked). A locked cache
To prevent locking during a cache access, a sync instruction must precede the setting of DLOCK.
20 ICFI Instruction cache Flash invalidate
0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation begins
1 An invalidate operation is issued that marks the state of each instruction cache block as invalid.
For the e300 core, the proper use of the ICFI and DCFI bits is to set and clear them with two consecutive
mtspr operations.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
7-22
Table 7-2. e300 HID0 Bit Descriptions (continued)
operational performance and is transparent to software or any external hardware.
marked cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache
operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored
and all instruction fetches are propagated to the coherent system bus (CSB) as single-beat
transactions. For those transactions, however, ci reflects the state of the I bit in the MMU for that page
regardless of cache disabled status. ICE is zero at power-up.
cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache operations)
are ignored. In the disabled state for the L1 caches, the cache tag state bits are ignored and all data
read and write accesses are propagated to the CSB as single-beat transactions. For those
transactions, however, ci reflects the state of the I bit in the MMU for that page regardless of cache
disabled status. DCE is zero at power-up.
supplies data normally on a hit, but the access is treated as a cache-inhibited transaction on a miss.
On a miss, the transaction to the bus is single-beat; however, ci still reflects the state of the I bit in
the MMU for that page independent of cache locked or disabled status.
supplies data normally on a hit, but is treated as a cache-inhibited transaction on a miss. On a miss,
the transaction to the bus is single-beat; however, ci still reflects the state of the I bit in the MMU for
that page independent of cache locked or disabled status. A snoop hit to a locked L1 data cache
performs as if the cache were not locked. A cache block invalidated by a snoop remains invalid until
the cache is unlocked.
(usually the next cycle after the write operation to the register). The instruction cache must be
enabled for the invalidation to occur.
Cache access is blocked during this time. Setting ICFI clears all the valid bits of the blocks and the
PLRU bits to point to way L0 of each set.
Function
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