Receive Status Register (Rstat) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

Hide thumbs Also See for MPC8313E:

Table of Contents

Receive short frame mode. When set, enables the reception of frames shorter than 64 bytes.

0 Ethernet frames less than 64B in length are silently dropped.

1) Frames more than 16B and less than 64B in length are accepted upon a DA match.

Note that frames less than or equal to 16B in length are always silently dropped.

Exact match MAC address enable. If this bit is set, the MAC01ADDR1–MAC15ADDR1 and

MAC01ADDR2–MAC15ADDR2 registers are recognized as containing MAC addresses aliasing the

MAC's station address. Setting this bit therefore allows eTSEC to receive Ethernet frames having a

destination address matching one of these 15 addresses.

Receive Status Register (RSTAT)

The eTSEC writes to this register under the following conditions:

A frame interrupt event occurred on one or more RxBD rings

The receiver runs out of descriptors due to a busy condition on a RxBD ring

The receiver was halted because an error condition was encountered while receiving a frame

Writing 1 to any bit of this register clears it. Software should clear the QHLT bit to take eTSEC's receiver

function out of halt state for the associated queue.

Offset eTSEC1:0x2_4304; eTSEC2:0x2_5304

describes the fields of the RSTAT register.

QHLT0 RxBD queue 0 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does

not cause a QHLT0 to be set.). The current frame and all other frames directed to a halted queue are

discarded. A write with a value of 1 re-enables the queue for receiving.

0 This queue is enabled for reception. (That is, it is not halted)

1 All controller receive activity to this queue is halted.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Table 15-28. RCTRL Field Descriptions (continued)

QHLT0 QHLT1 QHLT2 QHLT3 QHLT4 QHLT5 QHLT6 QHLT7

Figure 15-24. RSTAT Register Definition

Table 15-29. RSTAT Field Descriptions

Figure 15-24

describes the definition for the RSTAT

Enhanced Three-Speed Ethernet Controllers

Table of Contents