Freescale Semiconductor MPC8313E Family Reference Manual page 896

Powerquicc ii pro integrated processor

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Enhanced Three-Speed Ethernet Controllers

Recognition of the following ethertypes for inner layer parsing

— LLC and SNAP header

— JUMBO and SNAP header

— MPLSU/MPLSM

For stack L2 (that is, more than one ethertypes) header, the Ethernet parser traverses through the header

until it finds the last valid ethertype or the ethertype is unsupported.

Ethernet header parser recognizes for stack L2 header.

Column—Current L2

Row—Next Supported L2

Note: * means that it is the next protocol

The L3 parser is enabled by RCTRL[PRSDEP] = 10 or 11. It begins when the Ethernet parser ends and a

valid IPv4/v6 ethertype is found. The L4 header is enabled by RCTRL[PRSDEP] = 11. It begins when the

L3 parser ends and a valid TCP/UDP next protocol is found and no fragment frame is found. The primary

functionalities of L3(IPv4/6) and L4(TCP/UDP) parsers are as follows:

IP recognition (v4/v6, ARP, encapsulated protocol)

IP header checksum verification

IPv4/6 over IPv4/6 (tunneling)—parse headers and find layer 4 protocol

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Table 15-152. Supported Stack L2 Ethernet Headers

Table 15-152

describes what the

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