Detailed Memory Map - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
15.5.2

Detailed Memory Map

The eTSEC memory mapped registers are accessed by reading and writing to an address comprised of the
base address (specified in IMMRBAR as defined in
address, plus the offset of the specific register to be accessed. Note that all memory-mapped registers must
only be accessed as 32-bit quantities.
Table 15-4 lists the offset, name, and a cross-reference to the complete description of each register. The
offsets to the memory map table are applicable to each eTSEC. Block base addresses are as follows:
• eTSEC1 starts at 0x2_4000 address offset
• eTSEC2 starts at 0x2_5000 address offset
In this table and in the register figures and field descriptions, the following access definitions apply:
• Reserved fields are always ignored for the purposes of determining access type.
• R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
• w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
• Mixed indicates a combination of access types.
• Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
eTSEC1
Offset
0x2_4000 TSEC_ID*—Controller ID register
0x2_4004 TSEC_ID2*—Controller ID register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-12
Table 15-3. Module Memory Map Summary
Address Offset
000–0FF eTSEC general control/status registers
100–2FF eTSEC transmit control/status registers
300–4FF eTSEC receive control/status registers
500–5FF MAC registers
600–7FF RMON MIB registers
800–8FF Hash table registers
900–AFF
B00–BFF DMA system registers
C00–C3F Lossless Flow Control registers
C40–DFF
E00–EFF 1588 Hardware Assist
Table 15-4. Module Memory Map
1
Name
eTSEC General Control and Status Registers
Function
—
—
Chapter 3, "Memory Map.") plus the block base
2
Access
R
R
Reset Section/Page
0x0124_0106 15.5.3.1.1/15-22
0x0030_00F0 15.5.3.1.2/15-23
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