Freescale Semiconductor MPC8313E Family Reference Manual page 43

Figure
Number
9-33 DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-50
10-1 Enhanced Local Bus Controller Block Diagram................................................................... 10-1
10-2 Base Registers (BRn) .......................................................................................................... 10-10
10-3 Option Registers (ORn) in GPCM Mode............................................................................ 10-13
10-4 Option Registers (ORn) in FCM Mode............................................................................... 10-15
10-5 Option Registers (ORn) in UPM Mode .............................................................................. 10-18
10-6 UPM Memory Address Register (MAR) ............................................................................ 10-19
10-7 UPM Mode Registers (MxMR)........................................................................................... 10-20
10-8 Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 10-22
10-9 UPM Data Register in UPM Mode (MDR) ........................................................................ 10-23
10-10 FCM Data Register in FCM Mode (MDR)......................................................................... 10-23
10-11 Special Operation Initiation Register (LSOR) .................................................................... 10-24
10-12 UPM Refresh Timer (LURT) .............................................................................................. 10-24
10-13 Transfer Error Status Register (LTESR) ............................................................................. 10-25
10-14 Transfer Error Check Disable Register (LTEDR) ............................................................... 10-27
10-15 Transfer Error Interrupt Enable Register (LTEIR).............................................................. 10-28
10-16 Transfer Error Attributes Register (LTEATR...................................................................... 10-29
10-17 Transfer Error Address Register (LTEAR) ......................................................................... 10-30
10-18 Transfer Error ECC Register (LTECCR) ............................................................................ 10-31
10-19 Local Bus Configuration Register....................................................................................... 10-31
10-20 Clock Ratio Register (LCRR) ............................................................................................. 10-33
10-21 Flash Mode Register ........................................................................................................... 10-34
10-22 Flash Instruction Register ................................................................................................... 10-36
10-23 Flash Command Register .................................................................................................... 10-36
10-24 Flash Block Address Register ............................................................................................. 10-37
10-25 Flash Page Address Register, Small Page Device (ORx[PGS] = 0) ................................... 10-37
10-26 Flash Page Address Register, Large Page Device (ORx[PGS] = 1) ................................... 10-38
10-27 Flash Byte Count Register .................................................................................................. 10-39
10-28 Flash ECC Blockn Register (FECC0–FECC3)................................................................... 10-40
10-29 Basic Operation of Memory Controllers in the eLBC ........................................................ 10-41
10-30 Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0) ........ 10-43
10-31 Basic eLBC Bus Cycle with LALE, TA, and LCSn ........................................................... 10-44
10-32 Enhanced Local Bus to GPCM Device Interface................................................................ 10-46
10-33 GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8) .............. 10-46
10-34 GPCM General Read Timing Parameters ........................................................................... 10-47
10-35 GPCM General Write Timing Parameters .......................................................................... 10-49
10-36 GPCM Basic Write Timing
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 4, 8).................. 10-51
10-37 GPCM Relaxed Timing Back-to-Back Reads
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8)10-53
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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