Freescale Semiconductor MPC8313E Family Reference Manual page 340

e300 Processor Core Overview
Bits Name
15 ILE Interrupt little-endian mode. When an interrupt occurs, this bit is copied into MSR[LE] to select the endian
mode for the context established by the interrupt.
16 EE External interrupt enable
0 The processor ignores external interrupts, system management interrupts, and decrementer interrupts.
1 The processor is enabled to take an external interrupt, system management interrupt, or decrementer
interrupt.
17 PR Privilege level
0 The processor can execute both user- and supervisor-level instructions
1 The processor can only execute user-level instructions
18 FP Floating-point available0The processor prevents dispatch of floating-point instructions, including floating-point
loads, stores, and moves.
1 The processor can execute floating-point instructions and can take floating-point enabled exception type
program interrupts.
19 ME Machine check enable
0 Machine check interrupts are disabled
1 Machine check interrupts are enabled
20 FE0 Floating-point exception mode 0
21 SE Single-step trace enable
0 The processor executes instructions normally
1 The processor generates a trace interrupt upon the successful completion of the next instruction
22 BE Branch trace enable
0 The processor executes branch instructions normally
1 The processor generates a trace interrupt upon the successful completion of a branch instruction
23 FE1 Floating-point exception mode 1
24 CE Critical interrupt enable
0 Critical interrupts disabled
1 Critical interrupts enabled; critical interrupt and rfci instruction enabled
The critical interrupt is an asynchronous implementation-specific interrupt. The critical interrupt vector offset is
0x00A00. The rfci instruction is implemented to return from these interrupt handlers. Also, CSRR0 and
CSRR1 are used to save and restore the processor state for critical interrupts.
25 IP Interrupt prefix. The setting of this bit specifies whether an interrupt vector offset is prepended with Fs or 0s.
In the following description, nnnnn is the offset of the interrupt.
0 Interrupts are vectored to the physical address 0x000 n_nnnn
1 Interrupts are vectored to the physical address 0xFFF n_nnnn
26 IR Instruction address translation
0 Instruction address translation is disabled
1 Instruction address translation is enabled
27 DR Data address translation
0 Data address translation is disabled
1 Data address translation is enabled
1
28–29 — Reserved. Full function. Bit 29 not reserved on e300c3.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
7-18
Table 7-1. MSR Bit Descriptions (continued)
Description
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