Data Toggle; Data Toggle Reset; Data Toggle Inhibit - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Universal Serial Bus Interface
The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0
device framework (Chapter 9). A functional stall is only used on non-control endpoints and can be enabled
in the device controller by setting the endpoint stall bit in the ENDPTCTRLn register associated with the
given endpoint and the given direction. In a functional stall condition, the device controller will continue
to return STALL responses to all transactions occurring on the respective endpoint and direction until the
endpoint stall bit is cleared by the DCD.
A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device
controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD
should enable the stall bits (both directions) as a pair. A single write to the ENDPTCTRLn register can
ensure that both stall bits are set at the same instant.
Any write to the ENDPTCTRLn register during operational mode must
preserve the endpoint type field (that is, perform a read-modify-write).
Table 16-85
describes the device controller stall response matrix.
SETUP packet received by a non-control endpoint
IN/OUT/PING packet received by a non-control endpoint
IN/OUT/PING packet received by a non-control endpoint
SETUP packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint
16.8.3.2

Data Toggle

Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe.
For more information on data toggle, refer to the Universal Serial Bus Revision 2.0 Specification.
16.8.3.2.1

Data Toggle Reset

The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by writing a '1' to the data toggle reset bit in the ENDPTCTRLn register. This should only be
necessary when configuring/initializing an endpoint or returning from a STALL condition.
16.8.3.2.2

Data Toggle Inhibit

This feature is for test purposes only and should never be used during normal device controller operation.
Setting the data toggle Inhibit bit active ('1') causes the USB_DR to ignore the data toggle pattern that is
normally sent and accept all incoming data packets regardless of the data toggle state.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-138
Table 16-85. Device Controller Stall Response Matrix
USB Packet
NOTE
Endpoint
Stall Bit.
N/A
'1
'0
N/A
'1
'0
Effect on
USB Response
STALL Bit.
None
STALL
None
STALL
None
ACK/NAK/NYET
Cleared
ACK
None
STALL
None
ACK/NAK/NYET
Freescale Semiconductor

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