Freescale Semiconductor MPC8313E Family Reference Manual page 424

DDR Memory Controller
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions (continued)
Bits Name
10–11 CKE_CNTL Clock enable control
Allows software to globally clear or set all CKE signals issued to DRAM. Once software has forced the value
driven on CKE, that value continues to be forced until software clears the CKE_CNTL bits. At that time, the
DDR controller continues to drive the CKE signals to the same value forced by software until another event
causes the CKE signals to change (such as, self refresh entry/exit, power down entry/exit).
00 CKE signals are not forced by software.
01 CKE signals are forced to a low value by software.
10 CKE signals are forced to a high value by software.
11 Reserved
12–15 — Reserved
16–31 MD_VALUE Mode register value
This field, which specifies the value that is presented on the memory address pins of the DDR controller
during a mode register set command, is significant only when this register is used to issue a mode register
set command or a precharge or precharge all command.
For a mode register set command, this field contains the data to be written to the selected mode register.
For a precharge command, only bit five is significant:
0 Issue a precharge command; MD_SEL selects the logical bank to be precharged
1 Issue a precharge all command; all logical banks are precharged
Table 9-17 shows how DDR_SDRAM_MD_CNTL fields should be set for each of the tasks described
above.
Field
MD_EN
SET_REF
SET_PRE
CS_SEL
MD_SEL Select mode register.
See
MD_VALUE Value written to mode
register
CKE_CNTL
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-26
Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields
Mode Register Set
1
0
0
Chooses chip select (CS)
.
Table 9-16
0
Description
Refresh Precharge
0
1
0
— Selects logical bank
— Only bit five is
significant. See
Table 9-16
0
Clock Enable Signals
Control
0 —
0 —
1 —
—
—
—
.
0 See Table 9-16
Freescale Semiconductor
.