Gtm Memory Map/Register Definition - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
Table 5-54. GTM External Signals—Detailed Signal Descriptions (continued)
Signal I/O
TOUT n O Global timer counter output signal. The GTM output a signal on the timer output pin TOUT n when the
reference value is reached.
Meaning
Timing Assertion/Negation—TOUT n changes occur on the rising edge of the timer input clock.
5.7.5

GTM Memory Map/Register Definition

The GTM programmable register map occupies 64 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All GTM registers are 8 or 16 bits wide, located on 8-bit or 16-bit address boundaries, and should only be
accessed as 8-bit or 16-bit quantities. All addresses used in this chapter are offsets from GPT Base, as
defined in Chapter 3, "Memory Map."
Table 5-55 shows the memory map of the GTM.
Offset
General Purpose (Global) Timer Module 1—Block Base Address 0x0_0500
0x00 Timer 1 and 2 global timers configuration register (GTCFR1)
0x01–0x03 Reserved
0x04 Timer 3 and 4 global timers configuration register (GTCFR2)
0x05–0x0F Reserved
0x10 Timer 1 global timers mode register (GTMDR1)
0x12 Timer 2 global timers mode register (GTMDR2)
0x14 Timer 1 global timers reference register (GTRFR1)
0x16 Timer 2 global timers reference register (GTRFR2)
0x18 Timer 1 global timers capture register (GTCPR1)
0x1A Timer 2 global timers capture register (GTCPR2)
0x1C Timer 1 global timers counter register (GTCNR1)
0x1E Timer 2 global timers counter register (GTCNR2)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-54
State Asserted/Negated—According to the programmed polarity by the corresponding
GTMDR n [OM n ].
1. Active-low pulse on TOUT n for one timer input clock cycle as defined by the
GTMDR n [ICLK n ] bits (GTMDR n [OM n ] = 1). Thus, TOUT n may be low for one general
system clock period, one general system slow go clock period, or one TIN n pin clock
cycle period.
2. Toggle the TOUT n pin (GTMDR n [OM n ] = 0). TOUT n begins or stops counting, depending
on the signal state and the configured mode.
Table 5-55. GTM Register Address Map
Register
Description
Access
R/W
—
R/W
—
R/W
R/W
R/W
R/W
Reset Section/
Value Page
0x00 5.7.5.1/5-55
— —
0x00 5.7.5.1/5-55
— —
0x0000 5.7.5.2/5-58
0xFFFF 5.7.5.3/5-60
0x0000 5.7.5.4/5-60
0x0000 5.7.5.5/5-60
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