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MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-28. DDR1 Address Multiplexing for 16-Bit Data Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
13 12 11 10 9
8
7
13 12 11 10 9
8
12 11 10 9
8
7
12 11 10 9
8
12 11 10 9
11 10 9
8
11 10 9
11 10 9
Address from Core Master
1 0
6
5
4
3
2
1
0
1
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
1
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
DDR Memory Controller
11 9 8 7 6 5 4 3 2 1 0
1 0
9 8 7 6 5 4 3 2 1 0
0
11 9
8
7
6
5
4
1
0
9
8
7
6
5
4
0
11 9
8
7
6
5
4
1
0
9
8
7
6
5
4
0
1
0
8
7
6
5
4
1
0
9
8
7
6
5
4
0
1
0
8
7
6
5
4
1
0
1
0
7
6
5
4
lsb
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
9-37
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