Interrupt/Bulk Endpoint Bus Response Matrix - Freescale Semiconductor MPC8313E Family Reference Manual

RX-dTD is complete when:
• All packets described in dTD were successfully received. *** Total bytes in dTD will equal zero
when this occurs.
• A short packet (number of bytes < maximum packet length) was received. *** This is a successful
transfer completion; DCD must check Total Bytes in dTD to determine the number of bytes that
are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes
received.
• A long packet was received (number of bytes > maximum packet size) OR (total bytes received >
total bytes specified). *** This is an error condition. The device controller will discard the
remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint is flushed and
the USBERR interrupt will become active.
On the successful completion of the packet(s) described by the dTD, the active bit in the dTD is cleared
and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is set, the
USB_DR will flush the endpoint/direction and cease operations for that endpoint/direction.
On the unsuccessful completion of a packet (see long packet above), the dQH is left pointing to the dTD
that was in error. In order to recover from this error condition, the DCD must properly re-initialize the dQH
by clearing the active bit and update the nextTD pointer before attempting to re-prime the endpoint.
All packet level errors such as a missing handshake or CRC error will be
retried automatically by the device controller.
There is no required interaction with the DCD for handling such errors.
16.8.3.4.1

Interrupt/Bulk Endpoint Bus Response Matrix

Table 16-88 shows the interrupt/bulk endpoint bus response matrix.
Setup
In
Out
Ping
Invalid
1
Force Bit Stuff Error.
2
NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the
USB variable length protocol then ACK.
SYSERR—System error should never occur when the latency FIFOs are correctly sized and
the DCD is responsive.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 16-88. Interrupt/Bulk Endpoint Bus Response Matrix
Not
Stall
Primed
Ignore Ignore
STALL NAK
STALL NAK
STALL NAK
Ignore Ignore
NOTE
Primed
Ignore
Transmit
2
Receive + NYET/ACK
ACK
Ignore
Universal Serial Bus Interface
Underflow Overflow
N/A N/A
1
BS Error N/A
N/A NAK
N/A N/A
Ignore Ignore
16-141