Aesu Data Size Register (Aesudsr); Aesu Reset Control Register (Aesurcr) - Freescale Semiconductor MPC8313E Family Reference Manual

0
Field
Reset
R/W
Addr
14.4.3.3

AESU Data Size Register (AESUDSR)

The AESU data size register (AESUDSR), shown in
message block. Acceptable sizes vary depending on the AES mode selected. In ECB, CBC, and CTR
mode, the message processed by the AESU must be a multiple of 128 bits; the AESU does not
automatically pad messages out to 128-bit blocks. In CCM mode, data size must be a multiple of 8 bits. In
XOR mode the data size must be a multiple of 256 bits (32 bytes). If an improper data size is written, a
data size error is generated. Only the lowest 3, 7, or 8 bits of the data size register are checked to determine
if there is a data size error. Since all upper bits are ignored, the entire message length (in bits) can be written
to this register.
The AESUDSR is cleared when the AESU is reset or re-initialized.
Writing to the AESUDSR signals the AESU to start processing data from the shared symmetric input FIFO
as soon as it is available. If the value of data size is modified during processing, a context error is
generated.
0
Field
Reset
R/W
Addr
14.4.3.4

AESU Reset Control Register (AESURCR)

The AESU reset control register (AESURCR), shown in
AESU, as defined by the three self-clearing bits.
0
Field
Reset
R/W
Addr
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
—
Figure 14-27. AESU Key Size Register (AESUKSR)
—
Figure 14-28. AESU Data Size Register (AESUDSR)
—
Figure 14-29. AESU Reset Control Register (AESURCR)
51
0
R/W
AESU 0x3_4008
Figure 14-28, stores the number of bits in the final
51
0
R/W
AESU 0x3_4010
Figure 14-29, allows three levels reset of just
0
R/W
AESU 0x3_4018
Security Engine (SEC) 2.2
52
Key Size (bytes)
52
Data Size (bits)
60 61 62
RI MI SR
63
63
63
14-43