Nand Flash Read Status Command Sequence Example; Nand Flash Read Identification Command Sequence Example - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Table 10-44. FCM Register Settings for Soft Reset (OR n [PGS] = 1) (continued)

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NAND Flash Read Status Command Sequence Example

An example of configuring FCM to execute a status read command to large-page NAND Flash is shown

10-45. This sequence does not require use of the shared FCM buffer RAM, but reads the NAND

Flash status into register MDR[AS0]. The sequence is initiated by writing FMR[OP] = 10 and issuing a

special operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete

interrupt (LTESR[CC]) if interrupts are enabled.

Table 10-45. FCM Register Settings for Status Read (OR n [PGS] = 1)

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An example of configuring FCM to execute a status ID command to large-page NAND Flash is shown in

10-46. This sequence does not require use of the shared FCM buffer RAM, but uses MDR to set up

a dummy address prior to the sequence, and then to receive the first 4 bytes of ID during the sequence. The

sequence is initiated by writing FMR[OP] = 10, and issuing a special operation to the bank. At the

conclusion of the sequence, eLBC will issue a command complete interrupt (LTESR[CC]) if interrupts are

enabled. MDR[AS3–AS0] then can be read to obtain the first 4 bytes of NAND Flash ID.

Table 10-46. FCM Register Settings for ID Read (OR n [PGS] = 1)

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MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

OP0 = CM0 = command 0;

OP1–OP7 = NOP

CMD0 = 0x70 = read status command; other commands unused

Status returned in AS0

OP0 = CM0 = command 0;

OP1 = RS = read status to MDR;

OP2–OP7 = NOP

CMD0 = 0x90 = read ID command; other commands unused

Enhanced Local Bus Controller

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