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13.4.3
PCI Protocol Fundamentals
The bus transfer mechanism on the PCI bus is called a burst. A burst is comprised of an address phase and
one or more data phases.
All signals are sampled on the rising edge of the PCI clock. Each signal has a setup and hold window with
respect to the rising clock edge, in which transitions are not allowed. Outside this aperture, signal values
or transitions have no significance.
13.4.3.1
Basic Transfer Control
PCI data transfers are controlled by the following signals:
•
PCI_FRAME is driven by an initiator to indicate the beginning and end of a transaction.
•
PCI_IRDY (initiator ready) is driven by an initiator, allowing it to force wait cycles.
•
PCI_TRDY (target ready) is driven by a target, allowing it to force wait cycles.
The bus is idle when both PCI_FRAME and PCI_IRDY are negated. The first clock cycle in which
PCI_FRAME is asserted indicates the beginning of the address phase. The address and the bus command
code are transferred in that cycle. The next cycle ends the address phase and begins the data phase.
During the data phase, data is transferred in each cycle that both PCI_IRDY and PCI_TRDY are asserted.
Once the PCI controller, as an initiator, has asserted PCI_IRDY, it does not change PCI_IRDY or
PCI_FRAME until the current data phase completes, regardless of the state of PCI_TRDY. Once the PCI
controller, as a target, has asserted PCI_TRDY or PCI_STOP it does not change PCI_DEVSEL,
PCI_TRDY, or PCI_STOP until the current data phase completes.
When the PCI controller (as a master) intends to complete only one more data transfer, PCI_FRAME is
negated and PCI_IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target
indicates it is ready (PCI_TRDY asserted) the bus returns to the idle state.
13.4.3.2
Addressing
The PCI specification defines three physical address spaces—memory, I/O, and configuration. The
memory and I/O address spaces are standard for all systems. The configuration address space supports the
PCI hardware configuration. Each PCI device decodes the address for each PCI transaction with each
agent responsible for its own address decode.
The information contained in the two lower address bits (AD1 and AD0) depends on the address space. In
the I/O address space, all 32 address/data lines provide the full byte address. AD[1:0] are used for the
generation of PCI_DEVSEL and indicate the least significant valid byte involved in the transfer. Once a
target has claimed an I/O access, it first determines if it can complete the entire access as indicated by the
byte enable signals. If all the selected bytes are not in the address range, the entire access should not be
completed; that is, the target should not transfer any data and should terminate the transaction with a
target-abort operation. See
In the configuration address space, accesses are decoded to a 4-byte address using AD[7:2]. An agent
determines if it is the target of the access when a configuration command is decoded, IDSEL is asserted,
and AD[1:0] are 0b00; otherwise, the agent ignores the current transaction. The PCI controller determines
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Section 13.4.3.6, "Bus Transactions,"
for more information.
PCI Bus Interface
13-47
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