Error Correcting Codes And The Spare Region - Freescale Semiconductor MPC8313E Family Reference Manual

banks control both small and large-page devices, a large-page 4 Kbyte buffer must be assigned to either
the first 4 or last 4 small-page buffers.
Bank Base Address
offset 0x1000
offset 0x2000
End of Bank
Figure 10-47. FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND Flash Devices
10.4.3.1.3

Error Correcting Codes and the Spare Region

The FCM's ECC engine makes use of data in the NAND Flash spare region to store pre-computed ECC
code words. ECC is calculated in a single pass over blocks of 512 bytes of data in the main region. The
setting of FMR[ECCM] determines the location of the 24-bit ECC in the spare region.
The basic ECC algorithm is depicted in
matrix having 8 columns (corresponding with the device bus IO[7:0] or IO[15:8]) and 512 rows
(corresponding with each byte in the ECC block).
ECC
block
The placement of ECC code words in relation to FMR[ECCM] is shown in
devices, only a single 512-byte main region is ECC-protected. For large-page devices, there are four
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
buffer #0/page 0
buffer #1/page 1
replicated FCM
buffer RAM
images in bank
Figure
byte 0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
byte 1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
byte 510
byte 511
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Figure 10-48. FCM ECC Calculation
4 Kbyte page buffer:
10-48. The stream of data bytes is considered to form a
Enhanced Local Bus Controller
2048-byte main region (FPAR[MS] = 0)
64-byte spare region (FPAR[MS] = 1)
1984-byte reserved region (FPAR[MS] = 1)
Figure 10-49. For small-page
10-63