Core Disable In Low Power Mode - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
In general, EXT_PWR_CTRL should only be toggled when going to D3Warm. This is according to
general MPC8313E definitions for power levels. However, the implementation is flexible and allows for
the assertion of EXT_PWR_CTRL even in D1 or D2 if desired.
PMC_PWR_OK Signal
PMC_PWR_OK is an external input indication that the VDD that was switched off in the device D3Warm
mode has returned to specified levels after a wake-up event occurs. If an external power switch device is
used (not a FET), it will typically provide such a signal. When a wake-up event occurs and PMC asserts
the EXT_PWR_CTRL signal to turn on power, it will wait until the PMC_PWR_OK signal is asserted
before it will proceed to wait for the e300 pll to lock. If there is no external source of PMC_PWR_OK,
that is, an external FET is used to switch power and there's no way to indicate that power is stable, then
the customer will not select PMC_PWR_OK in the I/O multiplexing configuration. In this case
PMC_PWR_OK will always be asserted to the PMC by the multiplexing logic and the user will need to
add additional time to the PMC reset counter to insure there is enough time for power to become stable
and for the e300 PLL to lock.
PMCCR1[POWER_OFF] Bit
The PMCCR1[POWER_OFF] bit is set when the user wants to remove power to a portion of the die in
low power mode (D3Warm). This bit also allows boot code to distinguish between boot from power-on
reset and boot from D3Warm. It is referenced relative to the IMMRBAR register value. If the IMMRBAR
register is modified from its default location (the device configuration registers are moved to a different
location in memory), boot software must take care to ensure it can still find the PMCCR1[POWER_OFF]
bit. It may be necessary before entering D3Warm to change the IMMRBAR register back to its default
location.
Debugger in Low Power Mode
In D3Warm, the JTAG debug logic is powered down such that JTAG debug accesses will not be possible.
The conditioning logic in D3Warm causes JTAG inputs (TDI) to be ignored and holds TDO constant. This
will cause JTAG accesses to time out.
SerDes
The SerDes PHY is kept in low power mode when SGMII mode is not selected through the reset
configuration word. The SerDes PHY can also be put in low power mode under software control by
clearing the PMCCR1[llpen] bit.
5.8.4 Initialization/Application Information
5.8.4.1

Core Disable in Low Power Mode

If the device is required to operate with the core permanently disabled, the following steps must be taken:
1. Initialize the device with the core enable.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor 5-93