Channel Interrupts; Channel Done Interrupt; Channel Error Interrupt; Channel Reset - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
14.5.2

Channel Interrupts

The channel can assert both DONE and ERROR interrupts to the controller. When the interrupt generation
conditions have been met, the channel will assert the appropriate interrupt. The status of the registered
channel interrupts is available in the controller interrupt status register. The channel does not have an
internal interrupt mask, but the controller can be programmed to block channel interrupts through its
interrupt mask register (see
14.5.2.1

Channel Done Interrupt

Whether and when a channel DONE interrupt is generated depends on the setting of the crypto-channel
configuration register NT and CDIE bits in the CCCR (see
Done Interrupt Enable) is set, the channel will generate an interrupt event after every successfully
completed descriptor (Notification Type set to Global), or after each successfully completed descriptor
with the DN (Done Notification) bit set in the header word of the descriptor.
Even if multiple Channel Done interrupt events are generated by the channel before the first can be cleared
by the host, the interrupt events are not lost. The controller queues channel done interrupts from the
channel (see Section 14.6.3, "Controller
14.5.2.2

Channel Error Interrupt

The channel error interrupt is generated when an error condition occurs during descriptor processing. The
channel error interrupt will be asserted as soon as the error condition is detected. The type of error
condition is reflected the ERROR field of the channel pointer status register (CPSR). Refer to
for a complete listing of error types.
14.5.2.3

Channel Reset

Channel reset is asserted when the host sets the RESET bit in the channel configuration register (CCR).
The effect of software reset on the channel varies according to what the channel is doing when the bit is set:
• If the RESET bit is set while the channel is requesting an EU assignment from the controller, the
channel will cancel its request by asserting the release output signals. The channel will then reset
all the registers, clear the RESET bit and return the control state machine to the idle state.
• If the RESET bit is set after the channel has been dynamically assigned an EU, the channel will
request a write from the controller to set the software reset bit of the EU. A write to reset the
secondary (MDEU) EU will also be requested if one has been reserved for snooping. The channel
will then assert the appropriate release output signal to notify the controller that the channel has
finished with the reserved EU(s). The channel will then reset all the registers, clear the RESET bit
and return the control state machine to the idle state.
14.6 Controller
The controller within the SEC is responsible for overseeing the operations of the execution units (EUs),
the interface to the host processor, and the management of the channels. The controller interfaces to the
host through the master/slave bus interface and to the channels and EUs through internal buses. All
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-64
Section 14.6.4.2, "Interrupt Mask Register
Interrupts").
(IMR)").
Figure 14-36). Assuming the CDIE (Channel
Table 14-35
Freescale Semiconductor