15.5.3.6.43 Transmit Fragment Counter (TFRG)
Figure 15-95
describes the definition for the TFRG register.
Offset eTSEC1:0x2_472C; eTSEC2:0x2_572C
0
R
W
Reset
Table 15-99
describes the fields of the TFRG register.
Bits
Name
0–19
—
Reserved
20–31 TFRG Transmit fragment counter. Increments for every frame less then 64 bytes, with an incorrect FCS value.
15.5.3.6.44 Carry Register 1 (CAR1)
Carry register bits are cleared on carry register writes when the respective bits are set.
describes the definition for the CAR1 register.
Offset eTSEC1:0x2_4730; eTSEC2:0x2_5730
0
1
2
R
C1
C1
C1
64
127
255
W w1c
w1c
w1c
Reset
16
17
18
R
C1
C1
C1
RPK
RFC
RMC
W w1c
w1c
w1c
Reset
Table 15-100
describes the fields of the CAR1 register.
Bits
Name
0
C164
1
C1127
2
C1255
3
C1511
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
—
Figure 15-95. Transmit Fragment Counter Register Definition
Table 15-99. TFRG Field Descriptions
3
4
5
C1
C1
C1
511
1K
MAX
MGV
w1c
w1c
w1c
19
20
21
C1
C1
C1
RBC
RXC
RXP
RXU
w1c
w1c
w1c
Figure 15-96. Carry Register 1 (CAR1) Register Definition
Table 15-100. CAR1 Field Descriptions
Carry register 1 TR64 counter carry bit
Carry register 1 TR127 counter carry bit
Carry register 1 TR255 counter carry bit
Carry register 1 TR511 counter carry bit
19 20
All zeros
Description
6
7
C1
w1c
All zeros
22
23
24
25
C1
C1
C1
C1
RAL
RFL
RCD
w1c
w1c
w1c
w1c
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
TFRG
Figure 15-96
13
—
26
27
28
29
C1
C1
C1
C1
RCS
RUN
ROV
RFR
w1c
w1c
w1c
w1c
31
Access: w1c
14
15
C1
C1
REJ
RBY
w1c
w1c
30
31
C1
C1
RJB
RDR
w1c
w1c
15-101