Freescale Semiconductor MPC8313E Family Reference Manual page 970

Universal Serial Bus Interface
Bits Name
23 PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
Host mode:
• The PHY can be put into low power suspend – when the downstream device has been put into suspend
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
Device mode:
• The PHY can be put into low power suspend – when the device is not running (USBCMD[RS] = 0b) or
suspend signaling is detected on the USB. Low power suspend is cleared automatically when the resume
signaling has been detected or when forcing port resume.
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USBDR_CLK signals, PHCD must be set and the following registers
should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0, ENDPTCTRL1,
ENDPTCTRL2.
22 WKOC Wake on over-current enable. Writing this bit to a one enables the port to be sensitive to over-current conditions
as wake-up events.
This field is zero if Port Power (PP) is zero.
This bit is used only in OTG/Host mode.
21 WKDS Wake on disconnect enable. Writing this bit to a one enables the port to be sensitive to device disconnects as
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is used only in OTG/Host mode.
20 WKCN Wake on connect enable. Writing this bit to a one enables the port to be sensitive to device connects as
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is used only in OTG/Host mode.
19–16 PTC Port test control. Any other value than zero indicates that the port is operating in test mode.
0000 Not Enabled
0001 J_STATE
0010 K_STATE
0011 SEQ_NAK
0100 Packet
0101 FORCE_ENABLE
0110–1111 Reserved, should be cleared
Refer to Chapter 7 of the USB Specification Revision 2.0 [3] for details on each test mode.
15–14 PIC Port indicator control. Control the link indicator signals. These signals are valid for host mode only.
00 Off
01 Amber
10 Green
11 Undefined
Refer to the USB Specification Revision 2.0 [3] for a description on how these bits are to be used.
This field is output from the module on the USB port control signals for use by an external LED driving circuit.
13 PO Port owner. Unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1
transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. System software uses this
field to release ownership of the port to a selected the module (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A
one in this bit means that an internal companion controller owns and controls the port.
Port owner hand-off is not implemented in this design, therefore this bit is always 0.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-28
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
Freescale Semiconductor