Ddr Sdram Initialization Sequence - Freescale Semiconductor MPC8313E Family Reference Manual

Table 9-37. Programming Differences between Memory Types (continued)
Parameter Description
RD_TO_PRE Read to Precharge
Timing
CKE_PLS Minimum CKE
Pulse Width
FOUR_ACT Four Activate
Window
RD_EN Registered DIMM
Enable
8_BE 8-beat burst enable DDR1
2T_EN 2T Timing Enable
ODT_CFG ODT Configuration DDR1
BSTOPR Burst To Precharge
Interval
9.6.2

DDR SDRAM Initialization Sequence

After configuration of all parameters is complete, system software must set
DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200 μs must elapse after
DRAM clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
DDR1 Should be set to 010 if burst length is 4 and 100 if burst
length is 8
DDR2 Should be set according to the specifications for the
memory used (t
RTP
for non-zero value of additive latency (AL) is a minimum of
AL + t cycles.
RTP
DDR1 Can be set to 001
DDR2 Should be set according to the specifications for the
memory used (t
CKE
DDR1 Should be set to 00001
DDR2 Should be set according to the specifications for the
memory used (t
FAW
DDR1 If registered DRAM modules are used, then this field
should be set to 1
DDR2 If registered DRAM modules are used, then this field
should be set to 1
If 8-beat bursts are desired, then this field should be set to
1
DDR2 Should be set to 0
DDR1 In heavily loaded systems, this can be set to 1 to gain extra
timing margin on the interface at the cost of
address/command bandwidth.
DDR2 In heavily loaded systems, this can be set to 1 to gain extra
timing margin on the interface at the cost of
address/command bandwidth.
Should be set to 00
DDR2 Can be set for termination at the IOs according to system
topology. Typically, if ODT is enabled, then the internal IOs
should be set up for termination only during reads to
DRAM.
DDR1 Can be set to any value, depending on the application.
Auto precharge can be enabled by setting this field to all
0s.
DDR2 Can be set to any value, depending on the application.
Auto precharge can be enabled by setting this field to all
0s.
Differences
). Time between read and precharge
)
). Only applies to eight logical banks.
DDR Memory Controller
Section/page
9.4.1.6/9-16
9.4.1.6/9-16
9.4.1.6/9-16
9.4.1.7/9-18
9.4.1.7/9-18
9.4.1.7/9-18
9.4.1.8/9-21
9.4.1.12/9-27
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