Transfer Error Attributes Register (Lteatr) - Freescale Semiconductor MPC8313E Family Reference Manual

Bits Name
5 WPI Write protect error interrupt enable.
0 Write protect error reporting is disabled.
1 Write protect error reporting is enabled.
6–7 — Reserved
8 WARA Write after read atomic (WARA) error interrupt enable.
0 WARA error reporting is disabled.
1 WARA error reporting is enabled.
9 RAWA Read after write atomic (RAWA) error interrupt enable.
0 RAWA error reporting is disabled.
1 RAWA error reporting is enabled.
10–11 — Reserved
12 CSI Chip select error interrupt enable.
0 Chip select error reporting is disabled.
1 Chip select error reporting is enabled.
13–29 — Reserved
30 UCCI UPM Run pattern command completion Event interrupt enable.
0 UPM Run pattern command completion reporting is disabled.
1 UPM Run pattern command completion reporting is enabled.
31 CCI FCM command completion Event interrupt enable.
0 Command completion reporting is disabled.
1 Command completion reporting is enabled.

10.3.1.12 Transfer Error Attributes Register (LTEATR)

The transfer error attributes register (LTEATR) captures source attributes of an error/event.
shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to allow LTESR,
LTEATR, and LTEAR to update following any subsequent events/errors.
LTEATR may not capture accurate information for errors that occur when
an FCM special operation is in progress.
Offset 0x0BC
0 2 3 4
R
— RWB
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 10-18. LTEIR Field Descriptions (continued)
10 11
— SRCID
Figure 10-16. Transfer Error Attributes Register (LTEATR
Description
NOTE
15 16 19 20
PB
All zeros
Enhanced Local Bus Controller
Figure 10-16
Access: Read/Write
23 24
BNK —
30 31
V
10-29