Timer Logic Overview; Time-Stamp Insertion On The Received Packets; Timestamp Point - Freescale Semiconductor MPC8313E Family Reference Manual

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Timer Logic Overview

The 1588 timer module can be partitioned into four different sub-modules as shown in

Every incoming packet's 8-byte time stamp is inserted into the packet data buffer as padding alignment

bytes. Time-stamp insertion into the data buffer requires RCTRL[PAL] to be set to a value greater than or

equal to 8 and the control bit RCTRL[TS] bit to be set.

The required timestamp point, as specified in the IEEE 1588 Specification Sep-2004 (IEC 61588 First

Edition), is shown in Figure 15-143. From this, it is clear that the end of the SFD is the critical point in the

MII data stream.

The sample point coincides with the cycle after the SFD (Start of Frame Delimiter) detection by the MAC.

For received frames, this will be at least 4 bit times (MII) or 8 bit times (GMII) after the message

timestamp point specified in [1588]. For transmission, the eTSEC sample point precedes the sample point

specified in [1588] by at least 4-bit times (MII) or 8-bit times (GMII). For a particular mode, the eTSEC

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

SFD Detection

Figure 15-142. 1588 Timer Design Partition

Message Timestamp

Start of Frame

Figure 15-143. Ethernet Sampling Points for 1588

Enhanced Three-Speed Ethernet Controllers

Ethernet MAC

Start of Frame

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