Gigabit Ethernet Controller Channel Operation; Hardware Controlled Initialization; User Initialization - Freescale Semiconductor MPC8313E Family Reference Manual

Table 15-140 describes the signals shared by all interfaces.
15.6.2

Gigabit Ethernet Controller Channel Operation

This section describes the operation of the eTSEC. First, the software initialization sequence is described.
Next, the software (Ethernet driver) interface for transmitting and receiving frames is reviewed. Frame
filtering and receive filing algorithm features are also discussed. The section concludes with interrupt
handling, inter-packet gap time, and loop back descriptions.
15.6.2.1 Initialization Sequence
This sections describes which registers are reset due to a hard or software reset and what registers the user
must initialize prior to enabling the eTSEC.
15.6.2.1.1

Hardware Controlled Initialization

A hard reset occurs when the system powers up. All eTSEC's registers and control logic are reset to their
default states after a hard reset has occurred. In this state, each eTSEC behaves like a PowerQUICC II Pro
device, except for the absence of out-of-sequence TxBD features. That is, initially TCP/IP off-load is
disabled and only single RxBD and TxBD rings are accessible.
15.6.2.1.2

User Initialization

After the system has undergone a hard reset, software must initialize certain basic eTSEC registers. Other
registers can also be initialized during this time, but they are optional and must be determined based on the
requirements of the system. See
for register initialization.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-140. Shared Signals
Signals I/O
MDIO I/O
MDC O
GTX_CLK125 I
Sum
Table 15-3 for the register list.
Table 15-141. Steps for Minimum Register Initialization
1. Set and clear MACCFG1 [Soft_Reset]
2. Initialize MACCFG2
3. Initialize MAC station address
4. Set up the PHY using the MII Mgmt Interface
5. Configure the GMII
No. of Signals
1 Management interface I/O
1 Management interface clock
1 Reference clock
Table 15-141
Description
Enhanced Three-Speed Ethernet Controllers
Function
—
describes the minimum steps
15-143