Freescale Semiconductor MPC8313E Family Reference Manual page 134

Memory Map
Offset
0x2_4E40 TMR_ALARM1_H*—Timer alarm 1 high register
0x2_4E44 TMR_ALARM1_L*—Timer alarm 1 high register
0x2_4E48 TMR_ALARM2_H*—Timer alarm 2 high register
0x2_4E4C TMR_ALARM2_L*—Timer alarm 2 high register
0x2_4E50– Reserved
0x2_4E7C
0x2_4E80 TMR_FIPER1*—Timer fixed period interval
0x2_4E84 TMR_FIPER2*—Timer fixed period interval
0x2_4E88 TMR_FIPER*3—Timer fixed period interval
0x2_4E8C-0 Reserved
x2_4E9F
0x2_4EA0 TMR_ETTS1_H*—Time stamp of general purpose
external trigger
0x2_4EA4 TMR_ETTS1_L*—Time stamp of general purpose external
trigger
0x2_4EA8 TMR_ETTS2_H*—Time stamp of general purpose
external trigger
0x2_4EAC TMR_ETTS2_L*—Time stamp of general purpose external
trigger
0x2_4EB0– Reserved
0x2_4FFF
0x2_5000– eTSEC2 registers
0x2_5FFF Note: eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to
0x2_4FFF except the offsets are from 0x 2_5000 to 0x2_5FFF.
0x3_0000– Reserved, should be cleared
0x3_0FFF
0x3_1008 IMR—Interrupt mask register
0x3_1010 ISR—Interrupt status register
0x3_1018 ICR—Interrupt clear register
0x3_1020 ID—Identification register
0x3_1028 EUASR—EU assignment status register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-28
Table 2-2. Memory Map (continued)
Register
eTSEC2 Registers
Security Engine Address Map Registers
Controller Registers
Access Reset
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W —
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
R/W 0xFFFF_FFFF
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0001_0000
— —
R/W 0x0000_0000
_0000_0000
R 0x0000_0000
_0000_0000
W 0x0000_0000
_0000_0000
R 0000_0000
_0000_00A0
R 0xF0F0_F0F0
_00FF_F0F0
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