Duart Register Descriptions; Receiver Buffer Registers (Urbr1 And Urbr) - Freescale Semiconductor MPC8313E Family Reference Manual

Offset
0x0_4501 UIER—ULCR[DLAB] = 0 UART1 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART1 divisor most significant byte register
0x0_4502 UIIR—ULCR[DLAB] = 0 UART1 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART1 FIFO control register
UAFR—ULCR[DLAB] = 1 UART1 alternate function register
0x0_4503 ULCR—ULCR[DLAB] = x UART1 line control register
0x0_4504 UMCR—ULCR[DLAB] = x UART1 MODEM control register
0x0_4505 ULSR—ULCR[DLAB] = x UART1 line status register
0x0_4506 UMSR—ULCR[DLAB] = x UART1 MODEM status register
0x0_4507 USCR—ULCR[DLAB] = x UART1 scratch register
0x0_4510 UDSR—ULCR[DLAB] = x UART1 DMA status register
0x0_4600 URBR—ULCR[DLAB] = 0 UART2 receiver buffer register
UTHR—ULCR[DLAB] = 0 UART2 transmitter holding register
UDLB—ULCR[DLAB] = 1 UART2 divisor least significant byte register
0x0_4601 UIER—ULCR[DLAB] = 0 UART2 interrupt enable register
UDMB—ULCR[DLAB] = 1 UART2 divisor most significant byte register
0x0_4602 UIIR—ULCR[DLAB] = 0 UART2 interrupt ID register
UFCR—ULCR[DLAB] = 0 UART2 FIFO control register
UAFR—ULCR[DLAB] = 1 UART2 alternate function register
0x0_4603 ULCR—ULCR[DLAB] = x UART2 line control register
0x0_4604 UMCR—ULCR[DLAB] = x UART2 MODEM control register
0x0_4605 ULSR—ULCR[DLAB] = x UART2 line status register
0x0_4606 UMSR—ULCR[DLAB] = x UART2 MODEM status register
0x0_4607 USCR—ULCR[DLAB] = x UART2 scratch register
0x0_4610 UDSR—ULCR[DLAB] = x UART2 DMA status register
18.3.1

DUART Register Descriptions

The following sections describe the UART1 and UART2 registers.
18.3.1.1 Receiver Buffer Registers (URBR1 and URBR2)
These registers contain the data received from the transmitter on the UART buses. In FIFO mode, when
read, they return the first byte received. For FIFO status information, refer to the UDSR[RXRDY]
description.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 18-3. DUART Register Summary (continued)
Register Access Reset Section/Page
R/W 0x00 18.3.1.4/18-8
R/W 0x00 18.3.1.3/18-6
R 0x01 18.3.1.5/18-9
W 0x00 18.3.1.6/18-10
R/W 0x00 18.3.1.7/18-11
R/W 0x00 18.3.1.8/18-12
R/W 0x00 18.3.1.9/18-14
R 0x60 18.3.1.10/18-14
R 0x00 18.3.1.11/18-16
R/W 0x00 18.3.1.12/18-16
R 0x01 18.3.1.13/18-17
R 0x00 18.3.1.1/18-5
W 0x00 18.3.1.2/18-6
R/W 0x00 18.3.1.3/18-6
R/W 0x00 18.3.1.4/18-8
R/W 0x00 18.3.1.3/18-6
R 0x01 18.3.1.5/18-9
W 0x00 18.3.1.6/18-10
R/W 0x00 18.3.1.7/18-11
R/W 0x00 18.3.1.8/18-12
R/W 0x00 18.3.1.9/18-14
R 0x60 18.3.1.10/18-14
R 0x00 18.3.1.11/18-16
R/W 0x00 18.3.1.12/18-16
R 0x01 18.3.1.13/18-17
DUART
18-5