Deu Status Register (Deusr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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14.4.1.5

DEU Status Register (DEUSR)

The DEU status register (DEUSR), displayed in
DEU internal signals. The DEUSR is read-only. Writing to this location will result in address error being
reflected in the DEU interrupt status register (DEUISR).
0
Field
Reset
R/W
Addr
Table 14-14
describes the DEUSR fields.
Bits
Name
0–39
Reserved
40–47
OFL
The number of dwords currently in the output FIFO
48–55
IFL
The number of dwords currently in the input FIFO
56–57
Reserved
58
HALT
Halt. Indicates that the DEU has halted due to an error.
0 DEU not halted
1 DEU halted
Note: Because the error causing the DEU to stop operating may be masked before reaching the interrupt
59–60
Reserved
61
IE
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 DEU is not signaling error
1 DEU is signaling error
62
ID
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 DEU is not signaling done
1 DEU is signaling done
63
RD
Reset done. This status bit, when high, indicates that DEU has completed its reset sequence, as reflected
in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the register,
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
39
40
47
48
OFL
Figure 14-11. DEU Status Register (DEUSR)
Table 14-14. DEUSR Field Descriptions
status register (ISR), the DEU interrupt status register (DEUISR) is used to provide a second source
of information regarding errors preventing normal operation.
(Section 14.6.4.3, "Interrupt Status Register
(Section 14.6.4.3, "Interrupt Status Register
indicating the EU is ready for operation.
Figure
14-11, contains 6 fields that reflect the state of
55
56
57
58
IFL
HALT
0
R
DEU 0x3_2028
Description
Security Engine (SEC) 2.2
59
60
61
62
IE
ID
(ISR)").
(ISR)").
63
RD
14-23

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