Freescale Semiconductor MPC8313E Family Reference Manual page 61

Table
Number
8-22 SERSR Field Descriptions .................................................................................................... 8-23
8-23 SERMR Field Descriptions................................................................................................... 8-24
8-24 SERCR Field Descriptions.................................................................................................... 8-25
8-25 SIFCR_H Field Descriptions ................................................................................................ 8-25
8-26 SIFCR_L Field Descriptions................................................................................................. 8-26
8-27 SEFCR Field Descriptions .................................................................................................... 8-26
8-28 SERFR Field Descriptions .................................................................................................... 8-27
8-29 SCVCR Field Descriptions ................................................................................................... 8-28
8-30 SMVCR Field Descriptions .................................................................................................. 8-28
8-31 Interrupt Source Priority Levels............................................................................................ 8-32
9-1 DDR Memory Interface Signal Summary .............................................................................. 9-3
9-2 Memory Address Signal Mappings......................................................................................... 9-4
9-3 Memory Interface Signals—Detailed Signal Descriptions ..................................................... 9-5
9-4 Clock Signals—Detailed Signal Descriptions ........................................................................ 9-7
9-5 DDR Memory Controller Memory Map................................................................................. 9-8
9-6 CSn_BNDS Field Descriptions............................................................................................. 9-10
9-7 CSn_CONFIG Field Descriptions ........................................................................................ 9-10
9-8 TIMING_CFG_3 Field Descriptions .................................................................................... 9-12
9-9 TIMING_CFG_0 Field Descriptions .................................................................................... 9-13
9-10 TIMING_CFG_1 Field Descriptions .................................................................................... 9-14
9-11 TIMING_CFG_2 Field Descriptions .................................................................................... 9-17
9-12 DDR_SDRAM_CFG Field Descriptions.............................................................................. 9-19
9-13 DDR_SDRAM_CFG_2 Field Descriptions.......................................................................... 9-21
9-14 DDR_SDRAM_MODE Field Descriptions.......................................................................... 9-23
9-15 DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 9-23
9-16 DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 9-24
9-17 Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 9-25
9-18 DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 9-26
9-19 DDR_DATA_INIT Field Descriptions ................................................................................. 9-27
9-20 DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 9-27
9-21 DDR_INIT_ADDR Field Descriptions ................................................................................ 9-28
9-22 DDR_IP_REV1 Field Descriptions ...................................................................................... 9-28
9-23 DDR_IP_REV2 Field Descriptions ...................................................................................... 9-29
9-24 Byte Lane to Data Relationship ............................................................................................ 9-34
9-25 Supported DDR1 SDRAM Device Configurations .............................................................. 9-34
9-26 Supported DDR2 SDRAM Device Configurations .............................................................. 9-35
9-27 DDR1 Address Multiplexing ................................................................................................ 9-36
9-28 DDR2 Address Multiplexing ................................................................................................ 9-37
9-29 Example of Address Multiplexing for 32-Bit Data Bus Interleaving Between
Two Banks........................................................................................................................ 9-37
9-30 DDR SDRAM Command Table............................................................................................ 9-39
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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