Freescale Semiconductor MPC8313E Family Reference Manual page 119

Offset
0x0_4600 UDLB—ULCR[DLAB] = 1 UART2 divisor least significant
byte register
0x0_4601 UIER—ULCR[DLAB] = 0 UART2 interrupt enable register
0x0_4601 UDMB_ULCR[DLAB] = 1 UART2 divisor most significant
byte register
0x0_4602 UIIR—ULCR[DLAB] = 0 UART2 interrupt ID register
0x0_4602 UFCR—ULCR[DLAB] = 0 UART2 FIFO control register
0x0_4602 UAFR—ULCR[DLAB] = 1 UART2 alternate function
register
0x0_4603 ULCR—ULCR[DLAB] = x UART2 line control register
0x0_4604 UMCR—ULCR[DLAB] = x UART2 MODEM control register
0x0_4605 ULSR—ULCR[DLAB] = x UART2 line status register
0x0_4606 UMSR—ULCR[DLAB] = x UART2 MODEM status register
0x0_4607 USCR—ULCR[DLAB] = x UART2 scratch register
0x0_4608– Reserved, should be cleared
0x0_460F
0x0_4610 UDSR—ULCR[DLAB] = x UART2 DMA status register
0x0_4700– Reserved, should be cleared
0x0_4FFF
0x0_5000 BR0—Base register 0
Note: Port size for BR0 is configured from the value of
RCWH[ROMLOC] which is loaded during reset,
hence 'RR' is either 0x08, 0x10, or 0x18.
0x0_5004 OR0—Options register 0
0x0_5008 BR1—Base register 1
0x0_500C OR1—Options register 1
0x0_5010 BR2—Base register 2
0x0_5014 OR2—Options register 2
0x0_5018 BR3—Base register 3
0x0_501C OR3—Options register 3
0x0_5020– Reserved, should be cleared
0x0_5064
0x0_5068 MAR—UPM address register
0x0_506C Reserved
0x0_5070 MAMR—UPMA mode register
0x0_5074 MBMR—UPMB mode register
0x0_5078 MCMR—UPMC mode register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 2-2. Memory Map (continued)
Register
Enhanced Local Bus Controller (eLBC) Registers
Access Reset
R/W 0x00
R/W 0x00
R/W 0x00
R 0x01
W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R 0x60
R 0x00
R/W 0x00
— —
R 0x01
— —
R/W 0x0000_RR01
R/W 0x0000_0FF7
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Memory Map
Section/Page
18.3.1.3/18-6
18.3.1.4/18-8
18.3.1.3/18-6
18.3.1.5/18-9
18.3.1.6/18-10
18.3.1.7/18-11
18.3.1.8/18-12
18.3.1.9/18-14
18.3.1.10/18-14
18.3.1.11/18-16
18.3.1.12/18-16
—
18.3.1.13/18-17
—
10.3.1.1/10-9
10.3.1.2/10-11
10.3.1.1/10-9
10.3.1.2/10-11
10.3.1.1/10-9
10.3.1.2/10-11
10.3.1.1/10-9
10.3.1.2/10-11
—
10.3.1.3/10-19
—
10.3.1.4/10-20
10.3.1.4/10-20
10.3.1.4/10-20
2-13