Hard Coded Reset Configuration Word Low Fields Values; Reset Configuration Load Fail; Default Reset Configuration Words - Freescale Semiconductor MPC8313E Family Reference Manual

Reset, Clocking, and Initialization
4.3.3.2.4

Reset Configuration Load Fail

Failure of reset configuration load by the I
2
structure or I C bus problem. If a reset configuration load failure occurs, due to preamble fail or any other
2
I C bus error detection, the device will continuously attempt to reload the hard reset configuration words
2
from the I C bus. The device does not negate HRESET and remains in hard reset state until the HRCWs
are successfully loaded or the PORESET flow is restarted.
4.3.3.3

Default Reset Configuration Words

If the device is configured not to load the reset configuration words from NOR Flash, NAND Flash, or an
2
I C EEPROM, it can also be initialized with one of five hard-coded default options, selected by the reset
configuration input signals, CFG_RESET_SOURCE[0:3]. In this mode, the device is assumed to be a PCI
agent, and therefore only clock modes differ among the four options.
The reset configuration words are driven internally with the values shown in
In this mode the device is also configured to accept PCI configuration cycles
when completing its reset sequence (In PCI function configuration register,
the CFG_LOCK bit is cleared). In addition, the inbound window size of the
PCI inbound window attribute registers (PIWARn[IWS]) is set to 0b010011,
defining 1-Mbyte (2
Function Configuration Register."
Table 4-23. Hard Coded Reset Configuration Word Low Fields Values
RCWL Bits:
Field: LBCM
LBC
Meaning:
controller
clock:
CFG_RESET_
csb_clk
SOURCE
0 1:1
Value
1 2:1
1000
1001
1010
1011
1100
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
4-26
2
C boot sequencer can be caused by an incorrect EEPROM data
(19+1)
) memory windows. See
0 1
DDRCM
DDR —
controller
clock:
csb_clk
0 1:1
1 2:1
0 1
0 1
0 1
0 1
0 1
NOTE
Section 13.3.3.24, "PCI
2–3 4–7
Res SPMF
csb_clk :
PCI_CLK
ratio
SPMF:1
10 0100
10 0010
10 0101
10 0010
10 0101
Table 4-23 and
8 9–15
Res COREPLL
— Core clock:
csb_clk ratio
0 0000100
0 0000101
0 0000011
0 0000100
0 0000100
Freescale Semiconductor
Table 4-24.
16–31
Res
—
16'b0
16'b0
16'b0
16'b0
16'b0