Freescale Semiconductor MPC8313E Family Reference Manual page 410

DDR Memory Controller
Offset 0x100
0
R
W
Reset
Figure 9-4. DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
Table 9-8 describes TIMING_CFG_3 fields.
Bits Name
0–12 —
13–15 EXT_REFREC
16–31 —
9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
DDR SDRAM timing configuration register 0, shown in
between various SDRAM control commands.
Offset 0x104
0 1 2 3 4 5
R
RWT WRT RRT WWT — ACT_PD_EXIT — PRE_PD_EXIT
W
Reset 0 0 0 0 0 0
Figure 9-5. DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-12
12 13
— EXT_REFREC
Table 9-8. TIMING_CFG_3 Field Descriptions
Reserved
Extended refresh recovery time (t
until an activate command is allowed. This field is concatenated with TIMING_CFG_1[REFREC] to
obtain a 7-bit value for the total refresh recovery. Note that hardware adds an additional 8 clock
cycles to the final, 7-bit value of the refresh recovery. t
that t is calculated as follows:
RFC
000 0 clocks
001 16 clocks
010 32 clocks
011 48 clocks
100 64 clocks
101 80 clocks
110 96 clocks
111 112 clocks
Reserved
6 7 8 9 11
0 0 0 0 0 1
15 16
All zeros
Description
). Controls the number of clock cycles from a refresh command
RFC
RFC
Figure 9-5, sets the number of clock cycles
12 13 15 16
—
0 0 0 1 0 0 0 0
Access: Read/Write
—
= {EXT_REFREC || REFREC} + 8, such
Access: Read/Write
19 20 23 24
ODT_PD_EXIT —
0 0 0 1 0 0 0 0 0 1 0 1
Freescale Semiconductor
31
27 28 31
MRS_CYC