System Error Control Register (Sercr) - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
Offset 0x44
0
R
W
Reset
Table 8-23 defines the bit fields of SERMR.
Bits Name
0–31 INT n Each implemented SERMR bit, listed in
The user masks an MCP by clearing and enables an interrupt by setting the corresponding SERMR bit.
When a masked MCP occurs, the corresponding SERSR bit is set, regardless of the setting of the SERMR
bit although no MCP request is passed to the core. The SERMR can be read by the user at any time.
Writes to unimplemented (reserved) bits are ignored; read = 0
8.5.15

System Error Control Register (SERCR)

SERCR, shown in Figure
either MCP_OUT or PCI_INTA in core-disable mode.
Offset 0x48
0
R
W
Reset
Table 8-24 defines the bit fields of SERCR.
Bits Name
0–30 — Write ignored, read = 0
31 MCPR MCP route. Route MCP request to either MCP_OUT or PCI_INTA (in core disable mode).
0 MCP routed to PCI_INTA (in core disable mode).
1 MCP routed to MCP_OUT (in core disable mode).
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-24
n (Implemented bits are listed in
INT
Implemented bits reset to ones; unimplemented (reserved) bits reset to zeros.
Figure 8-17. System Error Mask Register (SERMR)
Table 8-23. SERMR Field Descriptions
8-18, defines the control bits that route MCP requests in core disable mode to
Figure 8-18. System Error Control Register (SERCR)
Table 8-24. SERCR Field Descriptions
Table 8-21.)
Description
Table 8-21, corresponds to an external and an internal MCP source.
—
All zeros
Description
Access: Read/write
31
Access: Read/write
30 31
MCPR
Freescale Semiconductor