Mii Management Address Register (Miimadd) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Table 15-47 describes the fields of the MIIMCOM register.
Bits Name
0–29 — Reserved
30 Scan Cycle Scan cycle. This bit is cleared by default.
0 Normal operation.
1 The MII management continuously performs read cycles. This is useful for monitoring link fail, for
example.
31 Read Cycle Read cycle. This bit is cleared by default but is not self-clearing once set.
0 Normal operation.
1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the
PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register
Address]). The 0-to-1 transition of this bit also causes the MIIMIND[Busy] bit to be set. The read is
complete when the MIIMIND[Busy] bit clears. Data is returned in register MIIMSTAT[PHY Status].
15.5.3.5.8

MII Management Address Register (MIIMADD)

The MIIMADD register is written by the user.
Offset eTSEC1:0x2_4528
0
R
W
Reset
Table 15-48 describes the fields of the MIIMADD register.
Bits Name
0–18 —
19–23 PHY Address
24–26 —
27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Table 15-47. MIIMCOM Descriptions
—
Figure 15-44. MIIMADD Register Definition
Table 15-48. MIIMADD Field Descriptions
Reserved
This field represents the 5-bit PHY address field of Mgmt cycles. Up to 31 PHYs can be addressed
(0 is reserved). Its default value is 0x00.
Reserved
accessed. Its default value is 0x00.
Description
Figure 15-44 shows the MIIMADD register.
18 19
PHY Address
All zeros
Description
Access: Read/Write
23 24 26 27
Register
—
Address
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31