Ddr Sdram Refresh - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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shows the use of the WR_DATA_DELAY parameter.

Figure 9-29. Write Timing Adjustments Example for Write Latency = 1

DDR SDRAM Refresh

The DDR memory controller supports auto-refresh and self-refresh. Auto-refresh is used during normal

operation and is controlled by the DDR_SDRAM_INTERVAL[REFINT] value; self-refresh is used only

when the DDR memory controller is set to enter a sleep power management state. The REFINT value,

which represents the number of memory bus clock cycles between refresh cycles, must allow for possible

outstanding transactions to complete before a refresh request is sent to the memory after the REFINT value

is reached. If a memory transaction is in progress when the refresh interval is reached, the refresh cycle

waits for the transaction to complete. In the worst case, the refresh cycle must wait the number of bus clock

cycles required by the longest programmed access. To ensure that the latency caused by a memory

transaction does not violate the device refresh period, it is recommended that the programmed value of

REFINT be less than that required by the SDRAM.

When a refresh cycle is required, the DDR memory controller does the following:

1. Completes all current memory requests.

2. Closes all open pages with a PRECHARGE-ALL command to each DDR SDRAM bank with an

open page (as indicated by the row open table).

3. Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified by its chip

select) to refresh one row in each logical bank of the selected physical bank.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

DDR Memory Controller

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