Jtag Registers And Scan Chains - Freescale Semiconductor MPC8313E Family Reference Manual

Table 20-2. JTAG Test—Detailed Signal Descriptions (continued)
Signal I/O
TDO O JTAG test data output.
State
Meaning
Timing See IEEE 1149.1 specification for more details.
TMS I JTAG test mode select.
State
Meaning
Timing See IEEE 1149.1 specification for more details.
TRST I JTAG test reset.
State
Meaning
Timing See IEEE 1149.1 specification for more details.
20.3

JTAG Registers and Scan Chains

The bypass, boundary-scan, and instruction JTAG registers and their associated scan chains are mandatory
for compliance with the IEEE 1149.1 specification.
• Bypass register. The bypass register is a single-stage register used to bypass the boundary-scan
latches of the device during board-level boundary-scan operations involving components other
than the device. The use of the bypass register reduces the total scan string size of the
boundary-scan test.
• Boundary-scan registers. The JTAG interface provides a chain of registers dedicated to
boundary-scan operations. To be JTAG-compliant, these registers cannot be shared with any
functional registers of the device. The boundary-scan register chain includes registers controlling
the direction of the input/output drivers, in addition to the registers reflecting the signal value
received or driven.
The boundary-scan registers capture the input or output state of the device's signals during a
Capture_DR TAP controller state. When a data scan is initiated following the Capture_DR state,
the sampled values are shifted out through the TDO output while new boundary-scan register
values are shifted in through the TDI input. At the end of the data scan operation, the
boundary-scan registers are updated with the new values during an update_DR TAP controller
state.
• Instruction register. The 8-bit JTAG instruction register serves as an instruction and status register.
As TAP controller instructions are scanned in through the TDI input, the TAP controller status bits
are scanned out through the TDO output.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Asserted/Negated—The contents of the selected internal instruction or data register are shifted out
on this signal on the falling edge of TCK. Remains in a high-impedance state except when
scanning data.
Asserted/Negated—Decoded by the internal JTAG TAP controller to distinguish the primary
operation of the test support circuitry. An unterminated input appears as a high signal level to
the test logic due to an internal pull-up resistor.
Asserted—Causes asynchronous initialization of the internal JTAG TAP controller. Must be asserted
during power-on reset in order to properly initialize the JTAG TAP and for normal operation of
the device. An unterminated input appears as a high signal level to the test logic due to an
internal pull-up resistor.
Negated— Normal operation.
Description
JTAG/Testing Support
20-3