Freescale Semiconductor MPC8313E Family Reference Manual page 403

9.3.2 Detailed Signal Descriptions
The following sections describe the DDR SDRAM controller input and output signals, the meaning of their
different states, and relative timing information for assertion and negation.
9.3.2.1 Memory Interface Signals
Table 9-3 describes the DDR controller memory interface signals.
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions
Signal I/O
MDQ[0:31] I/O Data bus. Both input and output signals on the DDR memory controller.
O As outputs for the bidirectional data bus, these signals operate as described below.
Meaning
Timing Assertion/Negation—Driven coincident with corresponding data strobes (MDQS) signal.
I As inputs for the bidirectional data bus, these signals operate as described below.
Meaning
Timing Assertion/Negation—The DDR SDRAM drives data during a READ transaction.
MDQS[0:3] I/O Data strobes. Inputs with read data, outputs with write data.
O As outputs, the data strobes are driven by the DDR memory controller during a write transaction. The
memory controller always drives these signals low unless a read has been issued and incoming data
strobes are expected. This keeps the data strobes from floating high when there are no transactions on
the DRAM interface.
Meaning
Timing Assertion/Negation—If a WRITE command is registered at clock edge n , data strobes at the
I As inputs, the data strobes are driven by the external DDR SDRAMs during a read transaction. The data
strobes are used by the memory controller to synchronize data latching.
Meaning
Timing Assertion/Negation—If a READ command is registered at clock edge n , and the latency is
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State Asserted/Negated—Represent the value of data being driven by the DDR memory controller.
High impedance—No READ or WRITE command is in progress; data is not being driven by
the memory controller or the DRAM.
State Asserted/Negated—Represents the state of data being driven by the external DDR
SDRAMs.
High impedance—No READ or WRITE command in progress; data is not being driven by the
memory controller or the DRAM.
State Asserted/Negated—Driven high when positive capture data is transmitted and driven low
when negative capture data is transmitted. Centered in the data "eye" for writes;
coincident with the data eye for reads. Treated as a clock. Data is valid when signals
toggle. See Table 9-24
DRAM assert centered in the data eye on clock edge n + 1. See the JEDEC DDR
SDRAM specification for more information.
State Asserted/Negated—Driven high when positive capture data is received and driven low when
negative capture data is received. Centered in the data eye for writes; coincident with
the data eye for reads. Treated as a clock. Data is valid when signals toggle. See
Table 9-24 for byte lane assignments.
programmed in TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM
assert coincident with the data on clock edge n + m . See the JEDEC DDR SDRAM
specification for more information.
Description
for byte lane assignments.
DDR Memory Controller
9-5