Freescale Semiconductor MPC8313E Family Reference Manual page 401

• Support for up to eight posted refreshes
• Memory controller clock frequency of two times the SDRAM clock with support for sleep power
management
9.2.1 Modes of Operation
The DDR memory controller supports the following modes:
• 32-byte cache line wrap mode
• Dynamic power management mode. The DDR memory controller can reduce power consumption
by negating the SDRAM CKE signal when no transactions are pending to the SDRAM.
• Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory
controller to issue an auto-precharge command with every read or write transaction.
Auto-precharge mode can be enabled for separate chip selects by setting
CSn_CONFIG[AP_n_EN].
9.3 External Signal Descriptions
This section provides descriptions of the DDR memory controller's external signals. It describes each
signal's behavior when the signal is asserted or negated and when the signal is an input or an output.
9.3.1 Signals Overview
Memory controller signals are grouped as follows:
• Memory interface signals
• Clock signals
• Debug signals
Table 9-1 shows how DDR memory controller external signals are grouped. The device hardware
specification has a pinout diagram showing pin numbers. It also lists all electrical and mechanical
specifications.
Name
MDQ[0:31] Data bus
MDQS[0:3] Data strobes
MCAS Column address strobe
MA[14:0] Address bus
MBA[0:2] Logical bank address
MCS[0:1] Chip selects
MWE Write enable
MRAS Row address strobe
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-1. DDR Memory Interface Signal Summary
Function/Description
DDR Memory Controller
Reset Pins I/O
All zeros 32 I/O
All zeros 4 I/O
One 1 O
All zeros 15 O
All zeros 3 O
All ones 2 O
One 1 O
One 1 O
9-3