Freescale Semiconductor MPC8313E Family Reference Manual page 971

Bits Name
12 PP Port power. Represents the current setting of the switch (0=off, 1=on). When power is not available on a port
(that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, and so on.
When an over-current condition is detected on a powered port, the PP bit in each affected port is transitioned
by the host controller driver from a one to a zero (removing power from the port).
This feature is implemented in the host/OTG controller (PPC = 1).
In a device-only implementation port power control is not necessary, thus PPC and PP = 0.
11–10 LS Line status. Reflect the current logical levels of the USB D+ (bit 11) and D– (bit 10) signal lines. The use of line
status by the host controller driver is not necessary (unlike EHCI), because the connection of FS and LS is
managed by hardware.
00 SE0
10 J-state
01 K-state
11 Undefined
9 — Reserved, should be cleared
8 PR Port reset.
Host mode:
• When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision
2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior
is different from EHCI where the host controller driver is required to set this bit to a zero after the reset
duration is timed in the driver.
Device mode:
• This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
1 Port is in reset.
0 Port is not in reset.
This field is zero if Port Power(PP) is zero.
7 SUSP Suspend.
Host mode:
• The port enabled bit (PE) and suspend (SUSP) bit define the port states as follows:
0x Disable
10 Enable
11 Suspend
• When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The
blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written
to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change
until the port is suspended and that there may be a delay in suspending a port if there is a transaction
currently in progress on the USB.
• The module unconditionally sets this bit to zero when software clears the FPR bit. A write of zero to this bit
is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (that is,
port enabled bit is a zero) the results are undefined.
• This field is zero if Port Power (PP) is zero in host mode.
Device mode:
1 Port in suspend state.
0 Port not in suspend state. Default.
In device mode this bit is a read-only status bit.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
Universal Serial Bus Interface
16-29