Freescale Semiconductor MPC8313E Family Reference Manual page 235

SICRH[Bits] Value:
Bits Group Pin Function 0
7 ELBC
NOTE: CFG_LBIU_MUX_EN = 0 bypasses the register and selects function 0.
8–9 INTR_B
2
10–11 I C
12–13 ETSEC2_B TSEC2_COL
14–15 ETSEC2_C TSEC2_CRS
16–17 ETSEC2_D TSEC2_GTX_CLK
18–19 ETSEC2_E TSEC2_RX_CLK
20–21 ETSEC2_F TSEC2_RX_DV
22–23 ETSEC2_G TSEC2_RX_ER
TSEC2_TX_CLK
24 ETSEC1_B TSEC1_COL
TSEC1_CRS
TSEC1_GTX_CLK
TSEC1_RX_CLK
TSEC1_RX_DV
TSEC1_RXD3
TSEC1_RXD2
TSEC1_RXD1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 5-28. SICRH Bit Settings (continued)
0b0/0b00 0b1/0b01
Pin Function 1
LA10 TSEC_1588_CLK
LA11 TSEC_1588_GCLK
LA12 TSEC_1588_PP1
LA13 TSEC_1588_PP2
LA14 TSEC_1588_TRIG1
LA15 TSEC_1588_ALARM2
IRQ4 CKSTOP_IN
IIC1_SDA CKSTOP_OUT
IIC1_SCL CKSTOP_IN
IIC2_SDA PMC_PWR_OK
IIC2_SCL —
GTM1_TIN4/
GTM2_TIN3
GTM1_TGATE4/
GTM2_TGATE3
GTM1_TOUT4
GTM1_TIN2/
GTM2_TIN1
GTM1_TGATE2/
GTM2_TGATE1
GTM1_TOUT2
—
USBDR_TXDRXD0
USBDR_TXDRXD1
USBDR_TXDRXD2
USBDR_TXDRXD3
USBDR_TXDRXD4
USBDR_TXDRXD5
USBDR_TXDRXD6
USBDR_TXDRXD7
0b10
Pin Function 2
1
—
1
—
1
—
1
—
1
—
1
—
—
—
—
—
—
—
—
GTM2_TOUT3
—
—
GTM2_TOUT1
—
—
—
—
—
—
—
—
—
System Configuration
0b11
Reset
Value
Pin Function 3
—
—
—
—
—
—
GPIO[12]
TSEC_1588_TRIG1
TSEC_1588_ALARM2
GPIO[10]
GPIO[11]
GPIO[15] 00 RTBI
11 Else
GPIO[16] 00 RTBI
11 Else
GPIO[17] 00 RTBI
11 Else
GPIO[18] 00 RTBI
11 Else
GPIO[19] 00 RTBI
11 Else
GPIO[24] 00 RTBI
11 Else
GPIO[25]
— 0 RTBI
1 Else
—
—
—
—
—
—
—
1
00
00
—
5-25