Fcm Bank 0 Reset Initialization; Boot Block Loading Into The Fcm Buffer Ram - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Local Bus Controller

When the core begins accessing memory after system reset, LCS0 is asserted initially to load a 4-Kbyte

boot block into the FCM buffer RAM, but core instruction fetches occur from the buffer RAM.

FCM Bank 0 Reset Initialization

The boot chip-select also provides a programmable port size, which is configured during reset. The boot

chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it

can be used as any other chip-select register after the preferred address range is loaded into BR0. After the

first write to OR0, the boot chip-select can be restarted only with a hardware reset.

the initial values of the boot bank in the memory controller.

Table 10-38. Boot Bank Field Values after Reset for FCM as Boot Controller

If FCM is selected as the boot ROM controller from power-on-reset configuration, eLBC will

automatically load from bank 0 a single 4 Kbyte page of boot code into the FCM buffer RAM during

HRESET. The CPU can execute boot code directly from the FCM buffer RAM, but must ensure that any

further data read from the NAND Flash EEPROM is transferred under software control in order to

continue the bootstrap process.

Since OR0[AM] is initially cleared during reset, all CPU fetches to eLBC will access the FCM buffer

RAM, which appears in the memory map as a 4-Kbyte RAM. No NAND Flash spare regions are mapped

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

0000_0000_0000_0000_0

0000_0000_0000_0000_0

From RCWH[ROMLOC]

From por_cfg_scy[1:3]

Freescale Semiconductor

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