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10.4.4.1.3
Software Requests—RUN Command
Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory devices
have their own signal handshaking protocol to put them into special modes, such as self-refresh mode.
For these special cycles, the user creates a special RAM pattern that can be stored in any unused areas in
the UPM RAM. Then a RUN command is used to run the cycle. The UPM runs the pattern beginning at
the specified RAM location until it encounters a RAM word with its LAST bit set. The RUN command is
issued by setting MxMR[OP] = 11 and accessing UPMn memory region with any write transaction that
hits the corresponding UPM machine. MxMR[MAD] determines the starting address in the RAM array for
the pattern.
Note that transfer acknowledges (UTA bit in the RAM word) are ignored for software (RUN command)
requests, and hence the LAD signals remain high-impedance unless the normal initial LALE occurs or the
RUN pattern causes assertion of LALE to occur on changes to the RAM word AMX field.
10.4.4.1.4
Exception Requests
When the eLBC under UPM control initiates an access to a memory device and an exception occurs (bus
monitor time-out), the UPM provides a mechanism by which memory control signals can meet the device's
timing requirements without losing data. The mechanism is the exception pattern that defines how the
UPM negates its signals in a controlled manner.
10.4.4.2
Programming the UPMs
The UPM is a micro sequencer that requires microinstructions or RAM words to generate signal timings
for different memory cycles. Follow these steps to program the UPMs:
1. Set up BRn and ORn registers.
2. Write patterns into the RAM array.
3. Program MRTPR, LURT and MAMR[RFEN] if refresh is required.
4. Program MxMR.
Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with any write
transaction that hits the relevant chip select. The entire array is thus programmed by an alternating series
of writes: to MDR (RAM word to be written) each time followed by a read from MDR and then followed
by a (dummy) write transaction to the relevant UPM assigned bank. A read from MDR is required to
ensure that the MDR update has occurred prior to the (dummy) write transaction.
RAM array contents may also be read for debug purposes, for example, by alternating dummy read
transactions, each time followed by reads of MDR (when MxMR[OP] = 10).
MxMR/MDR registers should not be updated while dummy read/write
access is still in progress. If the MxMR[MAD] is incremented then the
previous dummy transaction is already completed.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
NOTE
Enhanced Local Bus Controller
10-77
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