Internal Memory Mapped Registers; Accessing Immr Memory From The Local Processor; Complete Immr Map - Freescale Semiconductor MPC8313E Family Reference Manual

Chapter 2
Memory Map
This chapter describes the MPC8313E memory map. The internal memory mapped registers are described,
including a complete listing of all memory mapped registers with cross references to the sections detailing
descriptions of each.
2.1

Internal Memory Mapped Registers

All of the memory mapped registers in the device are contained within a 1-Mbyte address region. To allow
for flexibility, the base address of the memory mapped registers is relocatable in the local address space.
The local address map location of this register block is controlled by the internal memory mapped registers
base address register (IMMRBAR), see
Register (IMMRBAR)",
2.2

Accessing IMMR Memory From the Local Processor

When the local e300 processor is used to configure IMMR space, the IMMR memory space should
typically be marked as cache-inhibited and guarded.
In addition, many configuration registers affect accesses to other memory regions; therefore, writes to
these registers must be guaranteed to have taken effect before accesses are made to the associated memory
regions.
To guarantee that the results of any sequence of writes to configuration registers are in effect, the final
configuration register write should be followed immediately by a read of the same register, and that should
be followed by a sync instruction. Then accesses can safely be made to memory regions affected by the
configuration register write.
2.3

Complete IMMR Map

Table 2-1 lists the memory-mapped register regions (windows). Unless stated otherwise in a particular
block, all accesses to and from the memory mapped registers must be made with 32-bit accesses. There is
no support for accesses of sizes other than 32 bits.
Reading from address locations which appear as reserved in the memory map table is not guaranteed to
return predictable data. Writing to address locations which appear as reserved in the memory map table is
not allowed and could lead to unpredictable behavior of the device. Reserved bits in non-reserved registers
will be read as zero unless the reset value of those bits is different due to internal logic considerations.
When writing to registers with reserved bits, those reserved bits should be cleared. By doing so, existing
software would be able to run on a future modified device in which some reserved bits were allocated for
enhanced modes. This would allow for maintaining the legacy functionality when set to zero.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Section 5.2.4.1, "Internal Memory Map Registers Base Address
for more information. The default value for IMMRBAR is 0xFF40_0000.
2-1