Gpcm Boot Chip-Select Operation - Freescale Semiconductor MPC8313E Family Reference Manual

(internal transfer acknowledge generation), but it is the only means by which an access can be terminated
if ORn[SETA] = 1.
In PLL bypass mode, the timing of LGTA is illustrated by the example in
LCLK
Address
LAD
LALE
A
TA
LGTA
LCS n
LBCTL
LOE
Figure 10-43. External Termination of GPCM Access (PLL Bypass Mode)
10.4.2.5

GPCM Boot Chip-Select Operation

Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
When the core begins accessing memory after system reset, LCS0 is asserted for every local bus access
until BR0 or OR0 is reconfigured.
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Latched Address
Figure
1st 2nd
Sample Sample
Point Point
Read Data
Enhanced Local Bus Controller
10-43.
10-57