Endpoint Control Register 0 (Endptctrl0)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

16.3.2.22 Endpoint Control Register 0 (ENDPTCTRL0)—Non-EHCI
Endpoint control register 0, shown in
will implement endpoint 0 as a control endpoint.
Offset 0x1C0
31
R
—
W
Reset 0 0 0 0 0 0 0 0
Table 16-31 describes the endpoint control register 0 fields.
Bits Name
31–24 — Reserved, should be cleared.
23 TXE TX endpoint enable. Endpoint zero is always enabled.
0 Disable
1 Enable
22–20 — Reserved, should be cleared.
19–18 TXT TX endpoint type. Endpoint zero is always a control endpoint (00).
17 — Reserved, should be cleared.
16 TXS TX endpoint stall. Software can write a one to this bit to force the endpoint to return a STALL handshake to the
Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon
receipt of a new SETUP request.
1 Endpoint stalled
0 Endpoint OK
15–8 — Reserved, should be cleared.
7 RXE RX endpoint enable. Endpoint zero is always enabled.
0 Disabled
1 Enabled
6–4 — Reserved, should be cleared.
3–2 RXT RX endpoint type. Endpoint zero is always a control endpoint (00).
1 — Reserved, should be cleared.
0 RXS RX endpoint stall
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will
continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of
a new SETUP request.
1 Endpoint stalled
0 Endpoint OK
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 16-25, is not defined in the EHCI specification. Every device
24 23 22 20 19 18 17
TXE TXT
—
1 0 0 0 0 0
Figure 16-28. Endpoint Control 0 (ENDPTCTRL0)
Table 16-31. ENDPTCTRL0 Register Field Descriptions
16 15
— TXS —
0 0 0 0 0 0 0 0 0 0
Description
Universal Serial Bus Interface
Access: Mixed
8 7 6 4 3 2 1
RXE RXT
— — RXS
1 0 0 0 0 0 0
0
0
16-39